1. Field of the Invention
The present invention relates to semiconductor storage devices, and particularly to a semiconductor storage device that has a user region and a redundancy region.
2. Description of the Background Art
In a semiconductor storage device having a nonvolatile memory (hereinafter referred to as a memory array) that contains faulty bits, the memory array includes a user region and a redundancy region. The user region is a region where user data is stored, and the redundancy region is a region where redundancy data is stored, such as error-correcting code, fault map, etc. For example, Japanese Patent Application Laid-Open No. 8-235028(1996) (hereinafter referred to as Patent Document 1) discloses a memory array configuration having a user region and a redundancy region.
In the memory array of Patent Document 1, each page includes a pair of a user region and a redundancy region. The redundancy region is provided as a region that is added to the user region. Each redundancy region functions for correction etc. of the user region that forms a pair with that redundancy region. The capacity of the redundancy region is much smaller than the capacity of the user region.
The memory array configuration of Patent Document 1 may require specialized circuitry for reading redundancy data from the redundancy regions. However, separately providing such specialized circuitry leads to increased manufacturing costs. It also requires extra tests for testing the specialized circuitry, which complicates the process of testing the semiconductor storage device.
Also, in the memory array configuration of Patent Document 1, the areas of the memory that are used as redundancy regions can function only to store redundancy data, and the areas of the memory that are used as user regions can function only to store user data.
That is, the memory areas serving as redundancy regions cannot be used as user regions, and the memory areas serving as user regions cannot be used as redundancy regions. It is therefore impossible to locate the redundancy regions in appropriate positions according to variations among individual memory arrays.